PXIE301鏄寳浜潚缈肩鎶€鐨勪竴娆惧熀浜�PXI Express绺界窔鏋舵(g貌u)鐨勯珮鎬ц兘鏁�(sh霉)鎿�(j霉)闋�(y霉)铏曠悊FMC杓夋澘锛屾澘鍗″叿鏈�1鍊�FMC锛�HPC锛夋帴鍙�锛�1鍊�X8 PCIe涓绘(j墨)鎺ュ彛锛屾澘鍗￠噰鐢�Xilinx鐨勯珮鎬ц兘Kintex-7绯诲垪FPGA浣滅偤瀵�(sh铆)鏅傝檿鐞嗗櫒锛屽(sh铆)鐝�(xi脿n)FMC鎺ュ彛鏁�(sh霉)鎿�(j霉)鐨勯噰闆�銆佽檿鐞�銆佷互鍙�PCI Express绺界窔鎺ュ彛鐨勮綁(zhu菐n)鎻�銆傛澘杓�1绲勭崹(d煤)绔嬬殑64浣�DDR3 SDRAM澶у閲忕珐瀛�銆傝┎鏉垮崱閫氶亷鎼級涓嶅悓鐨�FMC瀛愬崱锛屽彲蹇€熸惌寤鸿捣鍩轰簬PXI Express鍎€鍣ㄧ附绶氱殑椹�(y脿n)璀夊钩鑷�锛岃┎鏉垮崱鐐烘(bi膩o)婧�(zh菙n)3U PXI Express灏哄锛岄仼鍚堜簬妯�(bi膩o)婧�(zh菙n)姝愬紡PXIE姗�(j墨)绠�锛屽彲寤ｆ硾鎳�(y墨ng)鐢ㄤ簬闆烽仈(d谩)鑸囦腑闋讳俊铏熼噰闆嗐€佽闋诲湒鍍忛噰闆嗙瓑鍫存櫙銆�
鎶€琛�(sh霉)鎸囨(bi膩o)
鏉胯級FPGA瀵�(sh铆)鏅傝檿鐞嗗櫒锛�XC7K325T-2FFG900I锛�
涓绘(j墨)鎺ュ彛鎸囨(bi膩o)锛�
1.绗﹀悎PXIe妯�(bi膩o)婧�(zh菙n)锛屾敮鎸�PCI Express 2.0瑕�(gu墨)鑼�锛�
2.鏀寔PCIe gen2 x8@5Gbps/lane锛�
3.PCIe闆欏悜DMA鍌宠几甯跺锛�3.2GByte/s锛�
FMC鎺ュ彛鎸囨(bi膩o)锛�
1.妯�(bi膩o)婧�(zh菙n)FMC锛�HPC锛夋帴鍙�锛岀鍚�VITA57.1瑕�(gu墨)鑼冿紱
2.鏀寔x8 GTX@10Gbps/lane楂橀€熶覆琛岀附绶�锛�
3.鏀寔80灏�LVDS淇¤櫉锛�
4.鏀寔IIC绺界窔鎺ュ彛锛�
5.+3.3V/+12V/+VADJ渚涢浕锛屼緵闆诲姛鐜団墺15W锛�
6.鐛�(d煤)绔嬬殑VIO_B_M2C渚涢浕锛堝彲鐢卞瓙鍗℃彁渚涳級锛�
鍕曟厠(t脿i)瀛樺劜鎬ц兘锛�
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2.瀛樺劜瀹归噺锛氭渶澶ф敮鎸�4GByte DDR3 SDRAM锛�
鍏跺畠鎺ュ彛鎬ц兘锛�
1.1鍊嬮珮绮炬檪閻樺柈鍏�锛屾敮鎸�1璺鏅傞悩杓稿叆銆�2璺悓姝ユ檪閻樿几鍑�锛�
2.2璺�RS485鎺ュ彛锛�4璺�LVTTL杓稿叆銆�4璺�LVTTL杓稿嚭锛�
3.鏉胯級1鍊�FRAM瀛樺劜鍣�銆�1鍊�BPI Flash锛�
鐗╃悊鑸囬浕姘ｇ壒寰�
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3.鏁ｇ啽鏂瑰紡锛氶ⅷ(f膿ng)鍐锋暎鐔憋紱
鐠�(hu谩n)澧冪壒寰�
1.宸ヤ綔婧害锛�-20掳~锕�70掳C锛屽瓨鍎叉韩搴︼細-40掳~锕�85掳C锛�
2.宸ヤ綔婵曞害锛�5%~95%锛岄潪鍑濈祼(ji茅)
杌熶欢鏀寔
1.鍙伕闆嗘垚鏉跨礆杌熶欢闁嬬櫦(f膩)鍖咃紙BSP锛夛細
2.FPGA搴曞堡鎺ュ彛椹�(q奴)鍕�锛�
3.PCIe绺界窔鎺ュ彛闁嬬櫦(f膩)鍙婂叾椹�(q奴)鍕曠▼搴忥紱
4.鍙牴鎿�(j霉)瀹㈡埗闇€姹傛彁渚涘畾鍒跺寲绠楁硶鑸囩郴绲�(t菕ng)闆嗘垚锛�
鎳�(y墨ng)鐢ㄨ寖鍦�
1.闆烽仈(d谩)鑸囦腑闋讳俊铏熻檿鐞�锛�
2.杌熶欢鐒＄窔闆婚(y脿n)璀夊钩鑷猴紱
3.鍦栧舰鑸囧湒鍍忚檿鐞嗛(y脿n)璀夊钩鑷�锛�
